| Title | A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks |
| Author | |
| Publication Years | 2022-09
|
| DOI | |
| Source Title | |
| ISSN | 1558-0806
|
| Volume | 69Issue:9Pages:3619-3631 |
| Keywords | |
| URL | [Source Record] |
| Indexed By | |
| Language | English
|
| SUSTech Authorship | Others
|
| EI Accession Number | 20222612280659
|
| EI Keywords | Benchmarking
; Computation theory
; Computer architecture
; Computer hardware
; Convolution
; Data handling
; Deep neural networks
; Energy efficiency
; Network architecture
; Systolic arrays
|
| ESI Classification Code | Ergonomics and Human Factors Engineering:461.4
; Energy Conservation:525.2
; Information Theory and Signal Processing:716.1
; Computer Theory, Includes Formal Logic, Automata Theory, Switching Theory, Programming Theory:721.1
; Logic Elements:721.2
; Computer Systems and Equipment:722
; Data Processing and Image Processing:723.2
|
| Data Source | IEEE
|
| PDF url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9793397 |
| Citation statistics |
Cited Times [WOS]:1
|
| Document Type | Journal Article |
| Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/347863 |
| Department | SUSTech Institute of Microelectronics |
| Affiliation | 1.Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China 2.School of Microelectronics, Southern University of Science and Technology, Shenzhen, China |
| Recommended Citation GB/T 7714 |
Mingqiang Huang,Yucen Liu,Changhai Man,et al. A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2022,69(9):3619-3631.
|
| APA |
Mingqiang Huang.,Yucen Liu.,Changhai Man.,Kai Li.,Quan Cheng.,...&Hao Yu.(2022).A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.IEEE Transactions on Circuits and Systems I: Regular Papers,69(9),3619-3631.
|
| MLA |
Mingqiang Huang,et al."A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks".IEEE Transactions on Circuits and Systems I: Regular Papers 69.9(2022):3619-3631.
|
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| J106.A_High_Performa（4433KB） | Journal Article | 作者接受稿 | Restricted Access | CC BY-NC-SA | ||
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