Title | An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors |
Author | |
Corresponding Author | Hu, Yushen |
Publication Years | 2022-09-01
|
DOI | |
Source Title | |
ISSN | 0018-9383
|
EISSN | 1557-9646
|
Volume | 69Issue:10Pages:5574-5579 |
Abstract | Implementing in-memory computation, an artificial neural network (ANN) consisting of thin-film transistors (TFTs) monolithically integrated in each unit of an array of capacitors is constructed. Both single-gate and parallel, dual-gate (DG) TFTs are deployed. The capacitors and the DG TFTs serve as the respective memory and computational elements. The DG TFT offers the capability of amplifying a weak but relevant input signal and suppressing a strong but irrelevant input signal across a synaptic gap, and the storage of charge on the capacitor is pseudostatic because of the exceptionally low oFr-state leakage current of the accompanying address TFT built on a metal-oxide semiconductor. The feasibility of such an ANN is demonstrated using a 4 x 6 array for classifying a specific set of Tetris patterns. |
Keywords | |
URL | [Source Record] |
Indexed By | |
Language | English
|
SUSTech Authorship | Corresponding
|
Funding Project | Innovation and Technology Fund[GHP/013/19SZ]
; Science and Technology Program of Shenzhen[JCYJ20200109140601691]
|
WOS Research Area | Engineering
; Physics
|
WOS Subject | Engineering, Electrical & Electronic
; Physics, Applied
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WOS Accession No | WOS:000852217000001
|
Publisher | |
ESI Research Field | ENGINEERING
|
Data Source | Web of Science
|
PDF url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9877914 |
Citation statistics |
Cited Times [WOS]:1
|
Document Type | Journal Article |
Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/401571 |
Department | SUSTech Institute of Microelectronics |
Affiliation | 1.Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Peoples R China 2.Southern Univ Sci & Technol, Sch Microelect, Shenzhen 518055, Peoples R China 3.Hong Kong Univ Sci & Technol HKUST, Dept Elect & Comp Engn, Hong Kong, Peoples R China 4.Hong Kong Univ Sci & Technol HKUST, Shenzhen Res Inst, Hong Kong, Peoples R China |
First Author Affilication | SUSTech Institute of Microelectronics |
Corresponding Author Affilication | SUSTech Institute of Microelectronics |
Recommended Citation GB/T 7714 |
Hu, Yushen,Lei, Tengteng,Wang, Yuqi,et al. An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES,2022,69(10):5574-5579.
|
APA |
Hu, Yushen,Lei, Tengteng,Wang, Yuqi,Wang, Fei,&Wong, Man.(2022).An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors.IEEE TRANSACTIONS ON ELECTRON DEVICES,69(10),5574-5579.
|
MLA |
Hu, Yushen,et al."An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors".IEEE TRANSACTIONS ON ELECTRON DEVICES 69.10(2022):5574-5579.
|
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