中文版 | English
Title

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die

Author
DOI
Publication Years
2019-04-22
Source Title
Volume
Part F160-OFC 2019
Abstract
A 50 Gb/s PAM-4 Retimer-CDR + VCSEL driver is fully-integrated in a 40nm CMOS process. Measurement results demonstrate wide optical eye openings using a 16GHz bandwidth VCSEL, achieving > 4 dB extinction ratio and < 8 pJ/bit energy efficiency.
SUSTech Authorship
Others
Language
English
URL[Source Record]
Indexed By
EI Accession Number
20202208772052
EI Keywords
Optical fiber communication ; CMOS integrated circuits ; Pulse amplitude modulation ; Clock and data recovery circuits (CDR circuits) ; Optical fibers
ESI Classification Code
Energy Conservation:525.2 ; Electric Networks:703.1 ; Semiconductor Devices and Integrated Circuits:714.2 ; Optical Communication Systems:717.1 ; Fiber Optics:741.1.2
Scopus EID
2-s2.0-85065491612
Data Source
Scopus
Citation statistics
Cited Times [WOS]:0
Document TypeConference paper
Identifierhttp://kc.sustech.edu.cn/handle/2SGJ60CL/401731
DepartmentDepartment of Electrical and Electronic Engineering
Affiliation
1.Department of Microelectronics,Fudan University,Shanghai,201203,China
2.Institute of Semiconductors,Chinese Academy of Sciences,Beijing,100083,China
3.PhotonIC Technologies,Shanghai,201203,China
4.Department of Electrical and Electronic Engineering,Southern University of Science and Technology,Shenzhen,518055,China
Recommended Citation
GB/T 7714
Hu,Shang,Yao,Tingyu,Yin,Bozhi,et al. A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die[C],2019.
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