A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing

Li，Kai1; Mao，Wei1; Zhou，Junzhuo1; Li，Boyu1; Yang，Zhengke1; Yang，Shuxing1; Du，Laimin2; Huang，Sixiao1; Yu，Hao1

2022

10.1109/TCSII.2022.3183007

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   Impact Factor & Quartile

1549-7747

1558-3791

There is an emerging need to design multi-precision floating-point (FP) accelerators for high-performance-computing (HPC) applications. The commonly-used methods are based on high-precision-split (HPS) and low-precision-combination (LPC) structures, which suffer from low hardware utilization ratio and various multiple clock-cycle processing periods. In this paper, a new multi-precision FP processing element (PE) is developed with proposed bit-partitioning method. Minimized redundant bits and operands are achieved. The proposed PE supports 16× half-precision (FP16), 4× single-precision (FP32) and 1× double-precision (FP64) operations with 100% multiplication hardware utilization ratio. Besides, vector systolic structure is designed for PE array to increase the system-level throughput and energy efficiency. The proposed design is realized in a 28-nm process with 1.351-GHz clock frequency. Compared with the existing multi-precision FP methods, the proposed work exhibits the best energy-efficiency performance of 1193 GFLOPS/W at FP16, 317 GFLOPS/W at FP32 and 77.3 GFLOPS/W at FP64 with at least 22.3%, 30% and 3.3% improvement, respectively.

accelerator Adders Energy efficiency floating-point Hardware High performance computing HPC MAC Mathematical models Multi-precision PE Resource management systolic Systolic arrays vector

SCI ; CPCI-S ; EI

English

First

WOS:000859143700035

20222612278149

Adders ; Clocks ; Digital arithmetic ; Structural design ; Systolic arrays

Structural Design, General:408.1 ; Energy Conservation:525.2 ; Computer Theory, Includes Formal Logic, Automata Theory, Switching Theory, Programming Theory:721.1 ; Numerical Methods:921.6 ; Special Purpose Instruments:943.3

ENGINEERING

2-s2.0-85132770022

Scopus

1.School of Microelectronics, and Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China
2.

Li，Kai,Mao，Wei,Zhou，Junzhuo,et al. A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,2022:1-1.

Li，Kai.,Mao，Wei.,Zhou，Junzhuo.,Li，Boyu.,Yang，Zhengke.,...&Yu，Hao.(2022).A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,1-1.

Li，Kai,et al."A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2022):1-1.