| Title | Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA |
| Author | |
| DOI | |
| Publication Years | 2022
|
| Conference Name | 35th IEEE International System-on-Chip Conference (SOCC)
|
| ISSN | 2164-1676
|
| EISSN | 2164-1706
|
| ISBN | 978-1-6654-5986-0
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| Source Title | |
| Pages | 1-5
|
| Conference Date | 5-8 Sept. 2022
|
| Conference Place | Belfast, United Kingdom
|
| Publication Place | 345 E 47TH ST, NEW YORK, NY 10017 USA
|
| Publisher | |
| Abstract | The Semi-Global Matching (SGM) algorithms and their hardware accelerators, which emphasize stereo matching rather than occlusion filling, have been developed in the last few years. However, filling occlusions is indispensable for many real-world applications. This work presents a pixel-level pipeline architecture for the post-processing of SGM, which refines disparity through a left-right check, and multi-directional occlusion filling refinement. The hardware architecture based on optimization algorithms is on the Stratix-IV platform, and it consumes about 5720 LUTs, 12961 registers, and 2.15M bits of on-chip memory. The maximum working frequency can reach up to 95.15 MHz for the 640x480 resolution video and 128 disparity range with the power dissipation of 1.46 W and 320 frames per second processing speed. |
| Keywords | |
| SUSTech Authorship | First
|
| Language | English
|
| URL | [Source Record] |
| Indexed By | |
| Funding Project | Shenzhen Science and Technology Innovation Commission["JSGG20200102162401765","K2021390006","K2021390007"]
|
| WOS Research Area | Computer Science
; Engineering
|
| WOS Subject | Computer Science, Hardware & Architecture
; Engineering, Electrical & Electronic
|
| WOS Accession No | WOS:000885041700012
|
| Data Source | IEEE
|
| PDF url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9908134 |
| Citation statistics |
Cited Times [WOS]:0
|
| Document Type | Conference paper |
| Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/406463 |
| Department | SUSTech Institute of Microelectronics |
| Affiliation | 1.School of Microelectronics, Southern University of Science and Technology 2.Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China |
| First Author Affilication | SUSTech Institute of Microelectronics |
| First Author's First Affilication | SUSTech Institute of Microelectronics |
| Recommended Citation GB/T 7714 |
Yunhao Ma,Xiwei Fang,Pingcheng Dong,et al. Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2022:1-5.
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