An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks
Optimized deep neural network (DNN) models and energy-efficient hardware designs are of great importance in edge-computing applications. The neural architecture search (NAS) methods are employed for DNN model optimization with mixed-bitwidth networks. To satisfy the computation requirements, mixed-bitwidth convolution accelerators are highly desired for low-power and high-throughput performance. There exist several methods to support mixed-bitwidth multiply-accumulate (MAC) operations in DNN accelerator designs. The low-bitwidth-combination (LBC) method improves the low-bitwidth throughput with a large hardware cost. The high-bitwidth-split (HBS) method minimizes the additional logic gates for configuration. However, the throughput performance in the low-bitwidth mode is poor. In this work, a bit-split-and-combination (BSC) systolic accelerator is proposed. The BSC-based MAC unit is designed to support mixed-bitwidth operations with the best overall performance. Besides, interprocessing element (PE) systolic and intra-PE paralleled dataflow not only improves throughput performance in mixed-bitwidth modes, but also saves power performance for data transmission. The proposed work is designed and synthesized in a 28-nm process. The BSC MAC unit achieves a maximum 2.08
|ESI Research Field|
Cited Times [WOS]:0
|Document Type||Journal Article|
|Department||SUSTech Institute of Microelectronics|
1.Ministry of Education, School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Southern University of Science and Technology, Shenzhen, China
2.Department of Computer Science and Engineering, University of California at Merced, Merced, CA, USA
3.Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan
4.School of Microelectronics, Fudan University, Shanghai, China
5.Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China
|First Author Affilication||SUSTech Institute of Microelectronics|
|First Author's First Affilication||SUSTech Institute of Microelectronics|
Mao，Wei,Dai，Liuyao,Li，Kai,et al. An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2022,PP(99):1-13.
Mao，Wei.,Dai，Liuyao.,Li，Kai.,Cheng，Quan.,Wang，Yuhang.,...&Yu，Hao.(2022).An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,PP(99),1-13.
Mao，Wei,et al."An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS PP.99(2022):1-13.
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