中文版 | English
Title

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA

Author
Corresponding AuthorHao Yu
DOI
Publication Years
2022-02
Conference Name
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA)
Conference Date
2022-2
Conference Place
美国加利福尼亚州蒙特雷
SUSTech Authorship
First ; Corresponding
Data Source
人工提交
PDF urlhttps://dl.acm.org/doi/10.1145/3490422.3502343
Citation statistics
Cited Times [WOS]:0
Document TypeConference paper
Identifierhttp://kc.sustech.edu.cn/handle/2SGJ60CL/415787
DepartmentSUSTech Institute of Microelectronics
Affiliation
1.Southern University of Science and Technology
2.Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China
Corresponding Author AffilicationSouthern University of Science and Technology
Recommended Citation
GB/T 7714
Mingqiang Huang,Yucen Liu,Quan Cheng,et al. A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA[C],2022.
Files in This Item:
There are no files associated with this item.
Related Services
Fulltext link
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Export to Excel
Export to Csv
Altmetrics Score
Google Scholar
Similar articles in Google Scholar
[Mingqiang Huang]'s Articles
[Yucen Liu]'s Articles
[Quan Cheng]'s Articles
Baidu Scholar
Similar articles in Baidu Scholar
[Mingqiang Huang]'s Articles
[Yucen Liu]'s Articles
[Quan Cheng]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Mingqiang Huang]'s Articles
[Yucen Liu]'s Articles
[Quan Cheng]'s Articles
Terms of Use
No data!
Social Bookmark/Share
No comment.

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.