| Title | A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA |
| Author | |
| Corresponding Author | Hao Yu |
| DOI | |
| Publication Years | 2022-02
|
| Conference Name | ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA)
|
| Conference Date | 2022-2
|
| Conference Place | 美国加利福尼亚州蒙特雷
|
| SUSTech Authorship | First
; Corresponding
|
| Data Source | 人工提交
|
| PDF url | https://dl.acm.org/doi/10.1145/3490422.3502343 |
| Citation statistics |
Cited Times [WOS]:0
|
| Document Type | Conference paper |
| Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/415787 |
| Department | SUSTech Institute of Microelectronics |
| Affiliation | 1.Southern University of Science and Technology 2.Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China |
| Corresponding Author Affilication | Southern University of Science and Technology |
| Recommended Citation GB/T 7714 |
Mingqiang Huang,Yucen Liu,Quan Cheng,et al. A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA[C],2022.
|
| Files in This Item: | There are no files associated with this item. | |||||
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