A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS

Jian Yang1; Quan Pan2; Jun Yin1; Pui-In Mak1

2023

10.1109/TMTT.2023.3242333

IEEE Transactions on Microwave Theory and Techniques   Impact Factor & Quartile

1557-9670

1557-9670

This article reports a 2.0-to-7.4-GHz 16-phase single-loop delay-locked loop (DLL) with high phase accuracy and wide locking range. It features a cascode current splitting charge pump (CP) to effectively suppress the current mismatch and the phase-delay error among the 16-phase outputs. Also, the proposed lock detector (LD) resolves the false-and harmonic-locking issues, extending the detection range from 3T(REF)/2 to 8T(REF)/3. Fabricated in 40-nm CMOS, the prototyped DLL achieves low phase-delay errors of 0.50 ps (0.36(?)) at 2.0 GHz and 0.58 ps (1.55(?)) at 7.4 GHz, respectively. The DLL occupies a compact area of 0.0168 mm(2) and consumes 18.3 mW at 7.4 GHz under a 1.1-V supply; the result corresponds to a power efficiency of 0.15 mW/GHz/phase that compares favorably with the state of the art.

Charge pump (CP) clock generator delay-locked loop (DLL) locking range multiphase clock phase accuracy

SCI

English

Others

National Natural Science Foundation of China[62074074] ; Natural Science Foundation of Guangdong Province[2021A1515011266] ; Science and Technology Plan of Shenzhen["JCYJ20190809142017428","JCYJ20200109141225025"] ; Science and Technology Development Fund, Macau, SAR["0045/2020/AMJ","SKL-AMSV(UM)-2023-2025"]

Engineering

Engineering, Electrical & Electronic

WOS:000936314000001

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

IEEE

1.Department of ECE, Institute of Microelectronics and Faculty of Science and Technology, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China
2.Ministry of Education, School of Microelectronics and Engineering Research Center of Integrated Circuits for Next-Generation Communications, Southern University of Science and Technology, Shenzhen, China

Jian Yang,Quan Pan,Jun Yin,et al. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques,2023,PP(99):1-9.

Jian Yang,Quan Pan,Jun Yin,&Pui-In Mak.(2023).A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS.IEEE Transactions on Microwave Theory and Techniques,PP(99),1-9.

Jian Yang,et al."A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS".IEEE Transactions on Microwave Theory and Techniques PP.99(2023):1-9.