A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS

Leiming Wang; Xiongshi Luo; Dongfan Xu; Zhang Qiu; Yiyang Yan; Quan Pan

10.1109/APCCAS55924.2022.10090288

2022

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

978-1-6654-5080-5

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

333-336

11-13 Nov. 2022

Shenzhen, China

345 E 47TH ST, NEW YORK, NY 10017 USA

IEEE

This paper presents a 160-Gb/s PAM4 optical receiver implemented in 28-nm CMOS process. The receiver consists of an equalized inverter-based transimpedance amplifier (TIA), a proposed 2-stage cascode-based single-to-differential converter (S2D), and a 2-stage variable gain amplifier (VGA). Inductive peaking techniques are adopted in equalized TIA and S2D for broadening bandwidth. Consuming 58.79-mW power, the proposed receiver achieves a differential conversion gain of 76.1 dB Omega with 0.2-dB and 3.2 degrees imbalances in amplitude and phase, respectively.

PAM4 optical receiver transimpedance high speed

First

English

CPCI-S

NSFC["JCYJ20190809142017428","JCYJ20200109141225025"] ; NSFGP[62074074] ; null[2021A1515011266] ; null[K21799121]

Computer Science ; Engineering

Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic

WOS:000987045300069

IEEE

School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

Leiming Wang,Xiongshi Luo,Dongfan Xu,et al. A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2022:333-336.