Title | An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout |
Author | |
DOI | |
Publication Years | 2022
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Conference Name | IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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ISBN | 978-1-6654-5080-5
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Source Title | |
Pages | 1-5
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Conference Date | 11-13 Nov. 2022
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Conference Place | Shenzhen, China
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Publication Place | 345 E 47TH ST, NEW YORK, NY 10017 USA
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Publisher | |
Abstract | Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore's law and the bottleneck of Von-Neumann architecture. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, optimized CNN model is required and low-power fully parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit 1 similar to 8-bit operations are supported by bitwidth configuration scheme for implementing Neural Architecture Search (NAS)-optimized multi-bit CNNs. Besides, energy-efficient fully parallel readout is achieved by variation-reduction accumulation mechanism and low-power readout circuits. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for 1 similar to 8-bit operations when evaluating NAS-optimized multi-bitwidth CNNs. |
Keywords | |
SUSTech Authorship | First
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Language | English
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URL | [Source Record] |
Indexed By | |
Funding Project | National Key Research and Development Program of the Ministry of science and technology[2021YFE0204000]
; Guangdong Provincial Key Laboratory Program from the Department of Science and Technology of Guangdong Province[2021B1212040001]
; Shenzhen Science and Technology Program[KQTD20200820113051096]
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WOS Research Area | Computer Science
; Engineering
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WOS Subject | Computer Science, Hardware & Architecture
; Engineering, Electrical & Electronic
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WOS Accession No | WOS:000987045300108
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Data Source | IEEE
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PDF url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10090365 |
Citation statistics |
Cited Times [WOS]:0
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Document Type | Conference paper |
Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/527456 |
Department | SUSTech Institute of Microelectronics |
Affiliation | School of Microelectronics Southern University of Science and Technology, Shenzhen, China |
First Author Affilication | SUSTech Institute of Microelectronics |
First Author's First Affilication | SUSTech Institute of Microelectronics |
Recommended Citation GB/T 7714 |
Dingbang Liu,Wei Mao,Haoxiang Zhou,et al. An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2022:1-5.
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