中文版 | English
Title

An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout

Author
DOI
Publication Years
2022
Conference Name
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
ISBN
978-1-6654-5080-5
Source Title
Pages
1-5
Conference Date
11-13 Nov. 2022
Conference Place
Shenzhen, China
Publication Place
345 E 47TH ST, NEW YORK, NY 10017 USA
Publisher
Abstract
Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore's law and the bottleneck of Von-Neumann architecture. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, optimized CNN model is required and low-power fully parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit 1 similar to 8-bit operations are supported by bitwidth configuration scheme for implementing Neural Architecture Search (NAS)-optimized multi-bit CNNs. Besides, energy-efficient fully parallel readout is achieved by variation-reduction accumulation mechanism and low-power readout circuits. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for 1 similar to 8-bit operations when evaluating NAS-optimized multi-bitwidth CNNs.
Keywords
SUSTech Authorship
First
Language
English
URL[Source Record]
Indexed By
Funding Project
National Key Research and Development Program of the Ministry of science and technology[2021YFE0204000] ; Guangdong Provincial Key Laboratory Program from the Department of Science and Technology of Guangdong Province[2021B1212040001] ; Shenzhen Science and Technology Program[KQTD20200820113051096]
WOS Research Area
Computer Science ; Engineering
WOS Subject
Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS Accession No
WOS:000987045300108
Data Source
IEEE
PDF urlhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10090365
Citation statistics
Cited Times [WOS]:0
Document TypeConference paper
Identifierhttp://kc.sustech.edu.cn/handle/2SGJ60CL/527456
DepartmentSUSTech Institute of Microelectronics
Affiliation
School of Microelectronics Southern University of Science and Technology, Shenzhen, China
First Author AffilicationSUSTech Institute of Microelectronics
First Author's First AffilicationSUSTech Institute of Microelectronics
Recommended Citation
GB/T 7714
Dingbang Liu,Wei Mao,Haoxiang Zhou,et al. An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2022:1-5.
Files in This Item:
There are no files associated with this item.
Related Services
Fulltext link
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Export to Excel
Export to Csv
Altmetrics Score
Google Scholar
Similar articles in Google Scholar
[Dingbang Liu]'s Articles
[Wei Mao]'s Articles
[Haoxiang Zhou]'s Articles
Baidu Scholar
Similar articles in Baidu Scholar
[Dingbang Liu]'s Articles
[Wei Mao]'s Articles
[Haoxiang Zhou]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Dingbang Liu]'s Articles
[Wei Mao]'s Articles
[Haoxiang Zhou]'s Articles
Terms of Use
No data!
Social Bookmark/Share
No comment.

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.