南方科技大学知识苑(SUSTech KC): 外延结构、P型晶体管、集成电路以及电源管理芯片

Title	外延结构、P型晶体管、集成电路以及电源管理芯片
Alternative Title	Epitaxial structure, P-type transistor, integrated circuit and power management chip
Author	化梦媛; 陈俊廷
First Inventor	化梦媛
Original applicant	南方科技大学
First applicant	南方科技大学
Address of First applicant	518055 广东省深圳市南山区桃源街道学苑大道1088号
Current applicant	南方科技大学
Address of Current applicant	518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)
First Current Applicant	南方科技大学
Address of First Current Applicant	518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)
Application Number	CN202210573412.9
Application Date	2022-05-25
Open (Notice) Number	CN115020469A
Date Available	2022-09-06
Status of Patent	实质审查
Legal Date	2022-09-23
Subtype	发明申请
SUSTech Authorship	First
Abstract	本发明公开了一种外延结构、P型晶体管、集成电路以及电源管理芯片，其中外延结构包括基体以及在基体上形成的垂直堆叠结构，所述垂直堆叠结构包括依次层叠的第一P型区、P型沟道区以及第二P型区，所述第二P型区的一侧表面与所述基体的一侧表面接触；通过上述垂直堆叠的第一P型区、P型沟道区以及第二P型区的外延结构中，P型沟道区可以在不受光刻工艺的限制下，将沟道长度锐减至纳米范围。此外还可以通过调节P型沟道区掺杂浓度，实现对具有上述外延结构的常关型P型晶体管阈值电压的自由调控。
Other Abstract	The invention discloses an epitaxial structure, a P-type transistor, an integrated circuit and a power management chip, the epitaxial structure comprises a substrate and a vertical stacking structure formed on the substrate, the vertical stacking structure comprises a first P-type region, a P-type channel region and a second P-type region which are stacked in sequence, one side surface of the second P-type region is in contact with one side surface of the substrate; in the epitaxial structure of the first P-type region, the P-type channel region and the second P-type region which are vertically stacked, the P-type channel region can sharply reduce the channel length to a nanometer range without being limited by a photoetching process. In addition, the threshold voltage of the normally-closed P-type transistor with the epitaxial structure can be freely regulated and controlled by adjusting the doping concentration of the P-type channel region.
CPC Classification Number	H01L29/1033 ; H01L29/0684 ; H01L27/088 ; H01L29/78 ; Y02B70/10
IPC Classification Number	H01L29/06 ; H01L29/10 ; H01L29/78 ; H01L27/088
INPADOC Legal Status	（ENTRY INTO FORCE OF REQUEST FOR SUBSTANTIVE EXAMINATION）[2022-09-23][CN]
INPADOC Patent Family Count	1
Extended Patent Family Count	1
Priority date	2022-05-25
Patent Agent	林青中
Agency	华进联合专利商标代理有限公司
URL	[Source Record]
Data Source	PatSnap
Document Type	Patent
Identifier	http://kc.sustech.edu.cn/handle/2SGJ60CL/531557
Department	Department of Electrical and Electronic Engineering
Recommended Citation GB/T 7714	化梦媛,陈俊廷. 外延结构、P型晶体管、集成电路以及电源管理芯片.

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