南方科技大学知识苑(SUSTech KC): 一种存内计算电路及方法

Title	一种存内计算电路及方法
Alternative Title	In-memory calculation circuit and method
Author	林龙扬; 孔镇; 李瑚淼 ; 李毅达; 周菲迟
First Inventor	林龙扬
Original applicant	南方科技大学
First applicant	南方科技大学
Address of First applicant	518055 广东省深圳市南山区西丽学苑大道1088号
Current applicant	南方科技大学
Address of Current applicant	518055 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)
First Current Applicant	南方科技大学
Address of First Current Applicant	518055 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)
Application Number	CN202210766593.7
Application Date	2022-07-01
Open (Notice) Number	CN115312090A
Date Available	2022-11-08
Status of Patent	实质审查 ; 一案双申
Legal Date	2022-11-25
Subtype	发明申请
SUSTech Authorship	First
Abstract	本发明公开了一种存内计算电路及方法，电路包括：n行n列设置的存储单元阵列；每列包括：若干并联的存储单元、数字‑时域脉冲信号转换器、充电单元、模数转换器与重置单元；存储单元为多比特阻变式存储单元；数字‑时域脉冲信号转换器用于将接收的输入操作数转换为时域脉冲信号并输出至存储单元；充电单元用于接收流过各个存储单元的电流进行充电以得到充电电压并输出至模数转换器；充电电压表示n个输入时域脉冲信号和n个存储单元电导值的乘加运算结果；模数转换器用于将乘加运算结果转换为数字码并输出；重置单元用于对充电单元的充电电压放电以重置运算周期。本发明在单个存储单元内可实现多比特存内计算，节省了占用面积，降低了功耗。
Other Abstract	The invention discloses an in-memory computing circuit and method. The circuit comprises a memory cell array arranged in n rows and n columns; each column comprises a plurality of parallel storage units, a digital-time domain pulse signal converter, a charging unit, an analog-to-digital converter and a reset unit; the memory unit is a multi-bit resistive memory unit; the digital-time domain pulse signal converter is used for converting the received input operand into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the charging unit is used for receiving current flowing through each storage unit for charging to obtain charging voltage and outputting the charging voltage to the analog-to-digital converter; the charging voltage represents a multiply-add operation result of the n input time domain pulse signals and the conductance values of the n storage units; the analog-to-digital converter is used for converting the multiply-add operation result into a digital code and outputting the digital code; the reset unit is used for discharging the charging voltage of the charging unit to reset the operation period. According to the invention, multi-bit in-memory calculation can be realized in a single memory unit, the occupied area is saved, and the power consumption is reduced.
IPC Classification Number	G11C8/08 ; G11C7/12 ; G06N3/08 ; G06N3/063 ; G06N3/04
INPADOC Legal Status	（ENTRY INTO FORCE OF REQUEST FOR SUBSTANTIVE EXAMINATION）[2022-11-25][CN]
INPADOC Patent Family Count	1
Extended Patent Family Count	2
Priority date	2022-07-01
Patent Agent	王永文
Agency	深圳市君胜知识产权代理事务所(普通合伙)
URL	[Source Record]
Data Source	PatSnap
Document Type	Patent
Identifier	http://kc.sustech.edu.cn/handle/2SGJ60CL/531598
Department	SUSTech Institute of Microelectronics 南方科技大学-香港科技大学深港微电子学院筹建办公室
Recommended Citation GB/T 7714	林龙扬,孔镇,李瑚淼,等. 一种存内计算电路及方法.

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