南方科技大学知识苑(SUSTech KC): 一种时钟同步电路、时钟同步方法和海底地震仪

Title	一种时钟同步电路、时钟同步方法和海底地震仪
Alternative Title	Clock synchronization circuit, clock synchronization method, and ocean bottom seismograph
Author	王宜志 ; 杨挺; 刘丹 ; 黄信峰; 黄志鹏; 潘谟晗; 杜浩然; 杨港
First Inventor	王宜志
Original applicant	南方科技大学
First applicant	南方科技大学
Address of First applicant	518000 广东省深圳市南山区西丽学苑大道1088号
Current applicant	南方科技大学
Address of Current applicant	518000 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)
First Current Applicant	南方科技大学
Address of First Current Applicant	518000 广东省深圳市南山区西丽学苑大道1088号 (广东,深圳,南山区)
Application Number	CN201910194086.9
Application Date	2019-03-14
Open (Notice) Number	CN109738954A
Date Available	2019-05-10
Status of Patent	实质审查 ; 许可
Legal Date	2019-06-04
Subtype	发明申请
SUSTech Authorship	First
Abstract	本发明公开了一种时钟同步电路、时钟同步方法和海底地震仪，其中，时钟同步电路包括：主时钟电路、至少一个地震数据采集电路、微处理器控制电路和至少两个分频电路；至少两个分频电路包括第一分频电路和第二分频电路；主时钟电路用于产生主时钟信号；第一分频电路与主时钟电路连接，用于对主时钟信号进行分频处理得到地震数据采集时钟信号；地震数据采集电路与第一分频电路连接，用于获取地震数据采集时钟信号；第二分频电路与主时钟电路连接，用于对主时钟信号进行分频处理得到实时时钟信号；微处理器控制电路与第二分频电路连接，用于获取所述实时时钟信号，本发明实施例提供的时钟同步电路时间精度高且功耗低。
Other Abstract	The invention discloses a clock synchronization circuit, a clock synchronization method, and an ocean bottom seismograph. The clock synchronization circuit comprises a main clock circuit, at least oneseismic data acquisition circuit, a microprocessor control circuit, and at least two frequency division circuits, wherein the at least two frequency division circuits comprise a first frequency division circuit and a second frequency division circuit; the main clock circuit is used to generate main clock signals; the first frequency division circuit is connected with the main clock circuit, and is used to carry out frequency division processing on the main clock signals to obtain seismic data acquisition clock signals; the seismic data acquisition circuit is connected with the first frequencydivision circuit and used to acquire the seismic data acquisition clock signals; the second frequency division circuit is connected with the main clock circuit, and is used to carry out frequency division processing on the main clock signals to obtain real-time clock signals; and the microprocessor control circuit is connected with the second frequency division circuit and used to acquire the real-time clock signals. The clock synchronization circuit provided by the embodiment of the invention has the advantages of high time accuracy and low power consumption.
CPC Classification Number	G01V1/38
IPC Classification Number	G01V1/38
INPADOC Legal Status	（ENTRY INTO FORCE OF RECORDATION OF PATENT LICENSING CONTRACT）[2021-09-10][CN]
INPADOC Patent Family Count	2
Extended Patent Family Count	2
Priority date	2019-03-14
Patent Agent	孟金喆
Agency	北京品源专利代理有限公司
URL	[Source Record]
Data Source	PatSnap
Document Type	Patent
Identifier	http://kc.sustech.edu.cn/handle/2SGJ60CL/532216
Department	Department of Ocean Science and Engineering
Recommended Citation GB/T 7714	王宜志,杨挺,刘丹,等. 一种时钟同步电路、时钟同步方法和海底地震仪.

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