| Title | 存储单元及其数据读写方法、制备方法及存储器 |
| Alternative Title | Storage unit, data read-write method and preparation method thereof and memory
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| Author | |
| First Inventor | 李毅达
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| Original applicant | 南方科技大学
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| First applicant | 南方科技大学
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| Address of First applicant | 518055 广东省深圳市南山区桃源街道学苑大道1088号
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| Current applicant | 南方科技大学
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| Address of Current applicant | 518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)
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| First Current Applicant | 南方科技大学
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| Address of First Current Applicant | 518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)
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| Application Number | CN202210417384.1
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| Application Date | 2022-04-20
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| Open (Notice) Number | CN114864582A
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| Date Available | 2022-08-05
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| Status of Patent | 实质审查
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| Legal Date | 2022-08-23
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| Subtype | 发明申请
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| SUSTech Authorship | First
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| Abstract | 本发明公开了一种存储单元及其数据读写方法、制备方法及存储器，存储单元包括：第一晶体管与第二晶体管；第一晶体管包括：第一栅极、位于第一栅极底面的第一介电层以及位于第一介电层底面的第一沟道层、第一源极与第一漏极；第二晶体管包括：第二栅极、位于第二栅极顶面的第二介电层以及位于第二介电层顶面的第二沟道层、第二源极与第二漏极；第二栅极与第一漏极连接；第二介电层包括：铁电层，铁电层位于第二源极与第二漏极的底面。本发明采用两个晶体管堆叠的存储单元结构进行数据读写，不仅消除了存储电容对尺寸缩小的影响，还避免了存储电容的结构互连的长度较长的问题，从而减小了互连线的距离，减小了电路延迟，提高了存储器的整体性能。 |
| Other Abstract | The invention discloses a memory cell, a data read-write method and a preparation method thereof, and a memory. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first grid electrode, a first dielectric layer located on the bottom surface of the first grid electrode, and a first channel layer, a first source electrode and a first drain electrode which are located on the bottom surface of the first dielectric layer; the second transistor comprises a second grid electrode, a second dielectric layer located on the top surface of the second grid electrode, and a second channel layer, a second source electrode and a second drain electrode which are located on the top surface of the second dielectric layer; the second grid electrode is connected with the first drain electrode; the second dielectric layer comprises a ferroelectric layer which is arranged on the bottom surfaces of the second source electrode and the second drain electrode. According to the invention, a storage unit structure formed by stacking two transistors is adopted for data reading and writing, so that the influence of a storage capacitor on size reduction is eliminated, and the problem that the interconnection length of the structure of the storage capacitor is relatively long is avoided, thereby reducing the distance of interconnection lines, reducing the circuit delay and improving the overall performance of the memory. |
| CPC Classification Number | H01L29/516
; G11C11/409
; G11C11/4099
; H10B12/30
; H10B12/05
; Y02D10/00
|
| IPC Classification Number | H01L27/108
; H01L29/51
; H01L21/8242
; G11C11/409
; G11C11/4099
|
| INPADOC Legal Status | （ENTRY INTO FORCE OF REQUEST FOR SUBSTANTIVE EXAMINATION）[2022-08-23][CN]
|
| INPADOC Patent Family Count | 1
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| Extended Patent Family Count | 1
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| Priority date | 2022-04-20
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| Patent Agent | 朱阳波
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| Agency | 深圳市君胜知识产权代理事务所(普通合伙)
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| URL | [Source Record] |
| Data Source | PatSnap
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| Document Type | Patent |
| Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/533019 |
| Department | SUSTech Institute of Microelectronics 前沿与交叉科学研究院 南方科技大学-香港科技大学深港微电子学院筹建办公室 |
| Recommended Citation GB/T 7714 |
李毅达,周冰,程振,等. 存储单元及其数据读写方法、制备方法及存储器.
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