双栅晶体管存储单元及存储器

Double-gate transistor memory cell and memory

李毅达; 周冰; 程振; 林龙扬; 张国飙; 沈美; 朱泉舟

李毅达

南方科技大学

南方科技大学

518055 广东省深圳市南山区桃源街道学苑大道1088号

南方科技大学

518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)

南方科技大学

518055 广东省深圳市南山区桃源街道学苑大道1088号 (广东,深圳,南山区)

CN202220939684.1

2022-04-20

CN217544163U

2022-10-04

2022-10-04

授权

2022-10-04

实用新型

First

本实用新型公开了双栅晶体管存储单元及存储器，其中，双栅晶体管存储单元包括：第一栅极；第一介电层，设置在所述第一栅极的顶面；沟道层，设置在所述第一介电层的顶面；源极与漏极，所述源极与所述漏极设置在所述第一介电层的顶面并位于所述沟道层两侧；其中，所述第一介电层包括铁电层，所述铁电层位于所述源极与所述漏极的底面；第二介电层，设置在所述沟道层的顶面；第二栅极，设置在所述第二介电层的顶面。本实用新型采用一个晶体管作为存储单元，消除了存储电容限制存储单元缩小面积的缺陷，使得铁电存储器可以很好的应用在三维集成技术中。

The utility model discloses a double-gate transistor memory cell and a memory, and the double-gate transistor memory cell comprises a first gate; the first dielectric layer is arranged on the top surface of the first grid electrode; the channel layer is arranged on the top surface of the first dielectric layer; the source electrode and the drain electrode are arranged on the top surface of the first dielectric layer and located on the two sides of the channel layer; wherein the first dielectric layer comprises a ferroelectric layer, and the ferroelectric layer is located on the bottom surface of the source electrode and the bottom surface of the drain electrode; the second dielectric layer is arranged on the top surface of the channel layer; and the second grid electrode is arranged on the top surface of the second dielectric layer. According to the utility model, a transistor is adopted as a memory unit, so that the defect that a memory capacitor limits the reduction of the area of the memory unit is eliminated, and the ferroelectric memory can be well applied to a three-dimensional integration technology.

G11C11/22

（+PATENT GRANT）[2022-10-04][CN]

1

1

2022-04-20

朱阳波

深圳市君胜知识产权代理事务所(普通合伙)

PatSnap

李毅达,周冰,程振,等. 双栅晶体管存储单元及存储器[P]. 2022-10-04.