Title | Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks |
Author | |
Publication Years | 2023
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DOI | |
Source Title | |
ISSN | 1558-0806
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Volume | PPIssue:99Pages:1-14 |
Keywords | |
URL | [Source Record] |
Indexed By | |
SUSTech Authorship | Others
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WOS Accession No | WOS:001051251100001
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Data Source | IEEE
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PDF url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10220121 |
Citation statistics |
Cited Times [WOS]:1
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Document Type | Journal Article |
Identifier | http://kc.sustech.edu.cn/handle/2SGJ60CL/559272 |
Department | SUSTech Institute of Microelectronics |
Affiliation | 1.Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan 2.School of Microelectronics, Southern University of Science and Technology, Shenzhen, China 3.School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA 4.Department of Electrical Engineering and Computer Science, University of California at Merced, Merced, CA, USA |
Recommended Citation GB/T 7714 |
Quan Cheng,Mingqiang Huang,Changhai Man,et al. Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2023,PP(99):1-14.
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APA |
Quan Cheng.,Mingqiang Huang.,Changhai Man.,Ao Shen.,Liuyao Dai.,...&Masanori Hashimoto.(2023).Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.IEEE Transactions on Circuits and Systems I: Regular Papers,PP(99),1-14.
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MLA |
Quan Cheng,et al."Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks".IEEE Transactions on Circuits and Systems I: Regular Papers PP.99(2023):1-14.
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