中文版 | English
Title

A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS

Author
Corresponding AuthorPan, Quan
DOI
Publication Years
2023
Conference Name
IEEE 49th European Solid-State Circuits Conference (ESSCIRC)
ISSN
1930-8833
Source Title
Conference Date
SEP 11-14, 2023
Conference Place
null,Lisbon,PORTUGAL
Publication Place
345 E 47TH ST, NEW YORK, NY 10017 USA
Publisher
Abstract
This work presents a quarter-rate 4-level pulse amplitude modulation (PAM-4) transmitter in 40-nm CMOS for vertical- cavity surface-emitting lasers (VCSELs). It adopts a thermometer code-based architecture with a 2-tap feed-forward equalizer (FFE) to independently control the gain and equalization strength of the top/middle/bottom (T/M/B) data slices for full compensation of VCSEL nonlinearities. Moreover, a pre-emphasis circuit is embedded within the continuous-time linear equalizer (CTLE) not only to mitigate the data eye skew caused by the VCSEL's asymmetric responses to rising and falling transitions, but also to extend the overall transmitter bandwidth. Optical measurement results demonstrate that with the 56-Gb/s PAM-4 data rate and 2.05-pJ/bit efficiency, the proposed piecewise nonlinearity compensation scheme improves the average sub-eye height/width and the ratio-of-level mismatch ( RLM) by 14%/12% and 38%, respectively, and the asymmetric equalization technique reduces the horizontal eye skew by 63%.
Keywords
SUSTech Authorship
Corresponding
Language
English
URL[Source Record]
Indexed By
Funding Project
Hong Kong RGC under the Areas of Excellence scheme grant[AoE/E-601/22-R] ; GRF[16205522] ; R&D Program in Key Areas of Guangdong Province[2019B010116002] ; Science and Technology Plan of Shenzhen["JCYJ20200109141225025","HC-CN-20210903005"]
WOS Research Area
Engineering ; Physics
WOS Subject
Engineering, Electrical & Electronic ; Physics, Applied
WOS Accession No
WOS:001088613100094
Data Source
Web of Science
Citation statistics
Document TypeConference paper
Identifierhttp://kc.sustech.edu.cn/handle/2SGJ60CL/582695
DepartmentSUSTech Institute of Microelectronics
Affiliation
1.Hong Kong Univ Sci & Technol, Opt Wireless Lab, Integrated Circuit Design Ctr, Hong Kong, Peoples R China
2.Southern Univ Sci & Technol, Sch Microelect, Shenzhen, Peoples R China
First Author AffilicationSUSTech Institute of Microelectronics
Corresponding Author AffilicationSUSTech Institute of Microelectronics
Recommended Citation
GB/T 7714
Chen, Fuzhan,Zhang, Chongyun,Wang, Li,et al. A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2023.
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